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ADE7518
Table 16. Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Bit
7
Address
0xFF
Mnemonic
FPSR
Default
0
Description
Power Supply Restored Interrupt Flag. Set when the V DD power supply has been restored.
This occurs when the source of V SWOUT changes from V BAT to V DD .
6
5
4
3
2
1
0
0xFE
0xFD
0xFC
0xFB
0xFA
0xF9
0xF8
FPSM
FSAG
Reserved
Reserved
Reserved
FBSO
FVDCIN
0
0
0
0
0
0
0
PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs.
Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs.
This bit must be kept cleared for proper operation.
This bit must be kept cleared for proper operation.
This bit must be kept cleared for proper operation.
Battery Switchover Interrupt Flag. Set when V SWOUT switches from V DD to V BAT.
V DCIN Monitor Interrupt Flag. Set when V DCIN falls below 1.2 V.
Table 17. Battery Switchover Configuration SFR (BATPR, 0xF5)
Bit
7 to 2
1 to 0
Mnemonic
Reserved
BATPRG[1:0]
Default
0
00
Description
These bits must be kept to 0 for proper operation.
Control Bits for Battery Switchover.
BATPRG[1:0] Result
00
01
1x
Battery switchover enabled on low V DD
Battery switchover enabled on low V DD and low V DCIN
Battery switchover disabled
Table 18. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit
7
6
5
4
Mnemonic
RXFLAG
VSWSOURCE
VDD_OK
PLL_FLT
Default
0
1
1
0
Description
If set, indicates that an Rx edge event triggered wake-up from PSM2.
Indicates the power supply that is internally connected to V SWOUT (0 V SWOUT = V BAT , 1 V SWOUT = V DD ).
If set, indicates that the V DD power supply is ready for operation.
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLL_FTL_ACK bit (see
Table 107) in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear
the PLL_FLT bit.
3
2
1 to 0
Reserved
Reserved
RXPROG[1:0]
0
0
00
This bit should be kept to 0.
This bit should be kept to 0.
Controls the function of the P1.0/RxD pin.
RXPROG[1:0] Result
00 GPIO
01
11
RxD with wake-up disabled
RxD with wake-up enabled
Table 19. Power Management Interrupt Enable SFR (IPSME, 0xEC)
Bit
7
6
5
4 to 2
1
0
Mnemonic
EPSR
Reserved
ESAG
Reserved
EBSO
EVDCIN
Default
0
0
0
0
0
0
Description
Enables a PSM interrupt when the power supply restored flag (FPSR) is set.
Reserved.
Enables a PSM interrupt when the voltage SAG flag (FSAG) is set.
These bits must be kept cleared for proper operation.
Enables a PSM interrupt when the battery switchover flag (FBSO) is set.
Enables a PSM interrupt when the V DCIN monitor flag (FVDCIN) is set.
Table 20. Scratch Pad 1 SFR (SCRATCH1, 0xFB)
Bit
7 to 0
Mnemonic
SCRATCH1
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Rev. 0 | Page 23 of 128
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